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Vinita

Tinkerboard 2S- UART- buildroot - output corrupted

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Hi,

  I am running a buildroot image with firefly deconfig on Tinkerboard 2S. It boots up but the output on UART is corrupted after it starts the kernel. Any advice to track down the issue.

[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
[    0.000005] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
[    0.010857] Console: colour dummy device 80x25
[    0.015740] printk: console [tty0] enabled
[    0.020243] printk: bootconsole [uart8250] disabled
FOfOFfFWgO.OFG_FGWWFfNfnF_WGFOGfVFVg^fof'ofwfF__WG7FOoF_WFGgGFG_G_WOwFW&gG_nnfF_w?GFv_F'7w_Wf_OfG_ffFfO�fFVF__Ff_Ffo�Nw_Fo"FGGo_FF_VRҒFV�F_OfwOoOVgfO_F_FgSGO/FFfGFOngOnfg_Fwg#g�Fwg�fOWfg6G_o�G_OF_O_gGW_O^gN^WOGWvOWFWFW_G.VgVO_gFfOF_F_F�GWoWNGFW_^_fGfWGNOfGOgNGo/_vFOFGGFOFgNOV?N_fCWFoWf_FON/N6g>nNG�_GNgWF�^G�G�NgFogGO"ggn_OWOf'G~GWWFwvnWWNW_f^/NoNFNgOVNOOngF~ofG_GOFGFWOF'._gOG_WWGoFo�o_oF_vVOFGgFOFFF~ggf_ffWN__NW~Fg_wFG_VgOFgv^�_VGVfGNgnCVG^oOVO_ofWo'Fg^?fWg~GFFOFOFVnGo6VG_GNOOfONOG_OoG�fO^ffOvNGO_WfOgwwv_Vf'O_Wvog^O^vW�^wVw�w�NOFOGvgGw_OvogO~wNWFoGgFw_ON_vw~_FOnGfWOFF_Ogn^~~^OG^Ow_OVOGVg_g�~~w~W~WvOWOgF_fGn�vVOGvOWOO^g_wGf~wv~vOf__G^f�fn'VwwgVGVvGfVGgVfOgWvWoWoOGVVONGgg6OVoCmbkVC[�2+G�T
dbRC�TMjL�DmEM[Vz}           RS�T
                  [
                   MGSSTMEOS2G"F#_OV_#jMVmEKKT_M2{MsWR_O2SKGDO*TWE]�VQFKO
                                                                         RGOODG�FdECWG_FT_[�fO#�D;[g]���";_b�OF~wF_VGG_�DGk�dRoF^WD2K�trMFDYS2C#vE4Dctc#_$tGG�GD�2SJFFDO�VG_"ZF�VWKDF_�FO�2WO[F^tG"F+_OF_OFW;_DKdgoV7Gv?Gg7V;S

 

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